open-eda-course/yosys-tutorial/yosys-tutorial.md at main · asinghani/open-eda-course

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Curriculum for a university course to teach chip design using open source EDA tools - asinghani/open-eda-course

Yosys Interactive Design Exploration Tutorial This tutorial is meant to be a starting point to learn how to use Yosys to interactively explore, analyze, and manipulate a digital logic design. You'll want to download the example SystemVerilog files in order to follow along. (These instructions have been tested with Yosys version 0.25+83, using the oss-cad-suite-linux-x64-20230125 build) Analyzing a SystemVerilog file Loading a file Let's start with this simple Verilog file counter4b.sv - just a 4 bit counter. Start yosys in interactive mode by running yosys in your shell. yosys>…

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Jianmin Chen

open-eda-course/yosys-tutorial/yosys-tutorial.md at main · asinghani/open-eda-course

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