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Some Simple Clock-Domain Crossing Solutions

zipcpu.com · 3,325 words · saved by 1 readers

In many ways, metastability is the big boogeyman within FPGA design. It is hard to see when desk-checking a design, it doesn’t show up on all simulations (certainly not with Verilator), your synthesis tool can’t solve it, and timing analysis often just gets in the way of dealing with it. Metastability, though, can make your design unreliable. If your design has a problem with metastability, then it might never work. It might work today and not tomorrow. It might work perfectly for months, and then have a fatal flaw.

In many ways, metastability is the big boogeyman within FPGA design. It is hard to see when desk-checking a design, it doesn’t show up on all simulations (certainly not with Verilator ), your synthesis tool can’t solve it, and timing analysis often just gets in the way of dealing with it. Metastability , though, can make your design unreliable. If your design has a problem with metastability , then it might never work. It might work today and not tomorrow. It might work perfectly for months, and then have a fatal flaw. In many ways, metastability problems are the worst of all errors. They are

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