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Adam Taylor’s MicroZed Chronicles, Part 70: Constraints—Introduction to timing and defining a clock

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Having introduced the basics of constraints within Vivado in my most recent blog posts, this post will focus upon timing constraints. At the most basic level within an FPGA, we use a clock to provide a regular timing reference upon which to transmit and receive data. If we were to analyze this by hand we would need to consider the clock period, set up (Tsu) and hold (Thd) times, and the clock-to-output (TclkQ) time to ensure that our design violates none of these times: We can check for timing violations by hand for a single register. However, as we implement complex designs within FPGAs containing millions of flip flops and complex, non-ideal clock trees, accounting for skew and jitter must be automated by the EDA tool—in this case the Vivado Design Suite; there are just too many things to check by hand. To understand timing constraints in Vivado we must first understand the terminology used to drive these constraints, as identified by Xilinx User guide UG903, “Vivado

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