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Lab 3: State and Registers | Computer Organisation and Program Execution
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Lab 3: State and Registers | Computer Architecture Search this site Search this site (powered by Google) Powered by Google Close search Skip table of contents On this page Outline Preparation Introduction Exercise 1: SR Latch Example Exercise 2: D Latch Clocks Exercise 3: D Flip-Flop Counter Exercise 4: Testing Sequential Circuits Exercise 5: Register File Special Case Registers Exercise 6: Memory Outline # The goals of this weeks lab are to: Understand the basic building blocks of sequential circuits Understand the clock input Understand the difference between level triggered and edge trigger
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