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research!rsc: Hardware Memory Models (Memory Models, Part 1)

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A long time ago, when everyone wrote single-threaded programs, one of the most effective ways to make a program run faster was to sit back and do nothing. Optimizations in the next generation of hardware and the next generation of compilers would make the program run exactly as before, just faster. During this fairy-tale period, there was an easy test for whether an optimization was valid: if programmers couldn't tell the difference (except for the speedup) between the unoptimized and optimized execution of a valid program, then the optimization was valid. That is, valid optimizations do not change the behavior of valid programs. One sad day, years ago, the hardware engineers' magic spells for making individual processors faster and faster stopped working. In response, they found a new magic spell that let them create computers with more and more processors, and operating systems exposed this hardware parallelism to programmers in the abstraction of threads. This new magic spell—multip

research!rsc: Hardware Memory Models (Memory Models, Part 1) research!rsc Thoughts and links about programming, by Russ Cox RSS Hardware Memory Models ( Memory Models , Part 1 ) Russ Cox June 29, 2021 research.swtch.com/hwmm Posted on Tuesday, June 29, 2021. PDF Introduction: A Fairy Tale, Ending A long time ago, when everyone wrote single-threaded programs, one of the most effective ways to make a program run faster was to sit back and do nothing. Optimizations in the next generation of hardware and the next generation of compilers would make the program run exactly as before, just faster. Du

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