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Design Tradeoffs

computationstructures.org · 4,218 words · saved by 1 readers

In many situations we can improve the average (or maximum) energy dissipation by choosing a design that minimizes the number of logic transitions per second. A simple way to achieve that goal is by lowering the clock frequency, usually at a proportional loss of processing performance; indeed, some modern computers have low-power operating modes which simply slow the clock to a fraction of its maximal rate. Assuming the requested operation is the exclusive or A ⊕ B 𝐴 ⊕ 𝐵 of two 32-bit input operands A 𝐴 and B 𝐵 , the 32-bit sum A + B 𝐴 + 𝐵 by the adder unit has simply wasted whatever power is taken for its computation. The redundant computation will automatically take place in our combinational circuit as soon as the A 𝐴 and B 𝐵 inputs take on new values, with many consequent transitions and power dissipation throughout the adder circuitry. This imposes a strict ordering on the component applications of the binary ⊛ ⊛ operator; it requires that the result of applyin

Design Tradeoffs lectures videos worksheets notes labs Contents Preliminaries 1. About this course 2. Engineering Abstraction Digital Circuits 3. Information 4. Circuits 5. The Digital Abstraction 6. CMOS 7. Combinational Logic 8. Sequential Logic 9. Finite State Machines 10. Synchronization and Arbitration 11. Performance Measures 12. Design Tradeoffs Programmable Architectures 13. Models of Computation 14. Instruction Set Architectures 15. Assembly Language 16. Stacks and Procedures 17. Compiled Languages 18. Processor Implementation 19. Memory Systems 20. Pipelined Processors Computer Syste

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