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highlights · 29
Statistical models for roundoff errors and A-D conversion errors, and linear system noise theory,
Quantization effects in digital filters | MIT Lincoln Laboratoryconstraint on signal level due to the requirement that overflow be prevented in the computation
Quantization effects in digital filters | MIT Lincoln Laboratoryerrors due to analog-digital (A-D) conversion
Quantization effects in digital filters | MIT Lincoln Laboratoryquantization of system coefficients
Quantization effects in digital filters | MIT Lincoln Laboratoryyou can take a set of sine waves of different amplitudes and frequencies and sum them together to equal any wave form.
DFT and FFT Tutorialthe binary file will be full of float32s in IQIQIQ order
File Sink - GNU RadioOne trick of this method, though, is that no new request can be made until the acknowledgement has been cleared.
Some Simple Clock-Domain Crossing Solutionsfrom a slow clock to a fast clock, from a fast clock to a slow clock, or even from one clock of unknown speed to another clock having no known relationship to the first. This calls for another approach: the handshaking method
Some Simple Clock-Domain Crossing SolutionsThe pull-up resistor is connected between the output pin and the output voltage (Vcc in the image above) that is desired for a high state.
What does "open drain" mean? - Semiconductor / Discrete Semiconductor Products - DigiKey TechForum - An Electronic Component and Engineering Solution ForumASIC designers, on the other hand, tend to like the active low reset.
Some Simple Clock-Domain Crossing Solutionsworks nicely for cases where the value from the old clock domain changes slowly–much slower than the frequency of the new clock domain’s clock.
Some Simple Clock-Domain Crossing Solutionsthe first one may have a high probability of metastability, the output of the second flip-flop has a much lower probability of metastability.
Some Simple Clock-Domain Crossing Solutionstwo flip-flops in this figure is clocked with the clock from the new clock domain,
Some Simple Clock-Domain Crossing SolutionsMetastability is caused when the set up and hold time requirements of a flip-flop aren’t met. The flip-flop then enters a state which is neither zero nor one, neither high nor low. It may be read by some of your logic as a zero, and by other parts of your logic as a one.
Some Simple Clock-Domain Crossing Solutionspy::object py_result = dnn_module.attr("DNN")(py_pilot_positions, py_pilot_values, len);
gr-digital/lib/ofdm_equalizer_simpledfe.cc · 356ce2461293635e9535e1e3580a08bd17940bd3 · dsp-chair-ip / mm-wave-mimo-trx-tb · GitLabCommon things a compiler does is to build a binary decision tree (saves compares and jumps in the average case) or simply build a jump-table (works without compares at all).
c++ - Advantage of switch over if-else statement - Stack OverflowModern compilers and their optimizers shouldn't differentiate between switch and an equivalent if-chain anymore.
c++ - Advantage of switch over if-else statement - Stack OverflowThe time complexity of this switch pattern should be O(1)
Something You May Not Know About the Switch Statement in C/C++ - CodeProjectwe are not able to determine the worst case in the switch execution, whether it would reach O(n) or not. Also we don't know under which conditions, the compiler chooses one implementation instead of another or even other methods unmentioned here.
Something You May Not Know About the Switch Statement in C/C++ - CodeProjectFrom the Documentation
How to create a new gitlab repo from my existing local git repo, using CLI? - Stack Overflowall you need is frequency synthesis then you're wasting a clock buffer.
FPGA, SystemVerilog, DesignsClock deskew is also known as phase alignment.
FPGA, SystemVerilog, Designsonly required if you need clock deskewing, that is a known, fixed phase relationship between the MMCM input clock and the MMCM output clock
FPGA, SystemVerilog, DesignsBUFG isn't needed if the source clock pin is connected directly to the MMCM and nothing else, but it is needed if there is other logic connected directly to the source clock pin.
fpga - Using MMCM/PLL source clock pin elsewhere in design breaks timing - Electrical Engineering Stack Exchange1. the problematic constraints in the .xdc generated by the clock wizard were commented out automatically, and 2. an additional BUFG was placed after the IBUF following the clock port, which wasn't present with the single ended option
fpga - Using MMCM/PLL source clock pin elsewhere in design breaks timing - Electrical Engineering Stack Exchangecreate_clock – period 10ns –name sys_clk –waveform {0 5} [get_ports sys_clk]
Adam Taylor’s MicroZed Chronicles, Part 70: Constraints—Introduction to timing and defining a clockthose that enter through an I/O pin
Adam Taylor’s MicroZed Chronicles, Part 70: Constraints—Introduction to timing and defining a clockNegative slack means metastability is an issue because of a timing violation.
Adam Taylor’s MicroZed Chronicles, Part 70: Constraints—Introduction to timing and defining a clockparsed header is not output as a stream, but as a PMT dictionary
Packet Header Parser - GNU Radio