Jon

on the atlas — 40

• The Road To Building a GPU - Part 1 - Blinking an LED - YouTube1 savers
• How to Use Coding Agents Effectively from Planning to Execution and Monitoring1 savers
• You can design a chip to run Kimi K3 at 87000 tps???6 savers
• Stanford CS229 Machine Learning | Spring 2026 - YouTube1 savers
• How Compiler Explorer Works in 2025 — Matt Godbolt’s blog2 savers
• Quantization effects in digital filters | MIT Lincoln Laboratory1 savers
• Inside NVIDIA GPUs: Anatomy of high performance matmul kernels - Aleksa Gordić9 savers
• Performance Hints11 savers
• AMD GPUs go brrr · Hazy Research1 savers
• Main1 savers
• srush/Tensor-Puzzles: Solve puzzles. Improve your pytorch.2 savers
• IQ Sampling | PySDR: A Guide to SDR and DSP using Python1 savers
• FFT: An 8 Input Butterfly1 savers
• DFT and FFT Tutorial1 savers
• Converting A Complex Wave To Fourier Series1 savers
• Maxime Heckel's Blog9 savers
• Craft3 savers
• MAKING SOFTWARE61 savers
• File Sink - GNU Radio1 savers
• Research1 savers
• What does "open drain" mean? - Semiconductor / Discrete Semiconductor Products - DigiKey TechForum - An Electronic Component and Engineering Solution Forum1 savers
• Some Simple Clock-Domain Crossing Solutions1 savers
• Discover, buy and download awesome fonts - Fonts Ninja1 savers
• About — Allison Chan1 savers
• Crossing the uncanny valley of conversational voice10 savers
• Andy McCune1 savers
• Tom Forsyth - The Lifecycle of an Instruction Set on Vimeo1 savers
• Understanding Matrix Multiplication on a Weight-Stationary Systolic Architecture | Telesens1 savers
• How To Scale Your Model34 savers
• udlbook6 savers
• CS231n Convolutional Neural Networks for Visual Recognition3 savers
• Build from Source - Install1 savers
• Google Deepmind – Bakken & Baeck1 savers
• Things You Learn Dating Cate Hall - by Sasha Chapin52 savers
• smallweb2 savers
• Git at any scale · Cursor16 savers
• TPU Deep Dive10 savers
• Dispatches from India8 savers
• What “Hardware is Hard” Really Means | eclecticc2 savers
• Omarchy — An opinionated Arch + Hyprland Setup by DHH2 savers

highlights — 29

• Statistical models for roundoff errors and A-D conversion errors, and linear system noise theory,

  Quantization effects in digital filters | MIT Lincoln Laboratory

• constraint on signal level due to the requirement that overflow be prevented in the computation

  Quantization effects in digital filters | MIT Lincoln Laboratory

• errors due to analog-digital (A-D) conversion

  Quantization effects in digital filters | MIT Lincoln Laboratory

• quantization of system coefficients

  Quantization effects in digital filters | MIT Lincoln Laboratory

• you can take a set of sine waves of different amplitudes and frequencies and sum them together to equal any wave form.

  DFT and FFT Tutorial

• the binary file will be full of float32s in IQIQIQ order

  File Sink - GNU Radio

• One trick of this method, though, is that no new request can be made until the acknowledgement has been cleared.

  Some Simple Clock-Domain Crossing Solutions

• from a slow clock to a fast clock, from a fast clock to a slow clock, or even from one clock of unknown speed to another clock having no known relationship to the first. This calls for another approach: the handshaking method

  Some Simple Clock-Domain Crossing Solutions

• The pull-up resistor is connected between the output pin and the output voltage (Vcc in the image above) that is desired for a high state.

  What does "open drain" mean? - Semiconductor / Discrete Semiconductor Products - DigiKey TechForum - An Electronic Component and Engineering Solution Forum

• ASIC designers, on the other hand, tend to like the active low reset.

  Some Simple Clock-Domain Crossing Solutions

• works nicely for cases where the value from the old clock domain changes slowly–much slower than the frequency of the new clock domain’s clock.

  Some Simple Clock-Domain Crossing Solutions

• the first one may have a high probability of metastability, the output of the second flip-flop has a much lower probability of metastability.

  Some Simple Clock-Domain Crossing Solutions

• two flip-flops in this figure is clocked with the clock from the new clock domain,

  Some Simple Clock-Domain Crossing Solutions

• Metastability is caused when the set up and hold time requirements of a flip-flop aren’t met. The flip-flop then enters a state which is neither zero nor one, neither high nor low. It may be read by some of your logic as a zero, and by other parts of your logic as a one.

  Some Simple Clock-Domain Crossing Solutions

• py::object py_result = dnn_module.attr("DNN")(py_pilot_positions, py_pilot_values, len);

  gr-digital/lib/ofdm_equalizer_simpledfe.cc · 356ce2461293635e9535e1e3580a08bd17940bd3 · dsp-chair-ip / mm-wave-mimo-trx-tb · GitLab

• Common things a compiler does is to build a binary decision tree (saves compares and jumps in the average case) or simply build a jump-table (works without compares at all).

  c++ - Advantage of switch over if-else statement - Stack Overflow

• Modern compilers and their optimizers shouldn't differentiate between switch and an equivalent if-chain anymore.

  c++ - Advantage of switch over if-else statement - Stack Overflow

• The time complexity of this switch pattern should be O(1)

  Something You May Not Know About the Switch Statement in C/C++ - CodeProject

• we are not able to determine the worst case in the switch execution, whether it would reach O(n) or not. Also we don't know under which conditions, the compiler chooses one implementation instead of another or even other methods unmentioned here.

  Something You May Not Know About the Switch Statement in C/C++ - CodeProject

• From the Documentation

  How to create a new gitlab repo from my existing local git repo, using CLI? - Stack Overflow

• all you need is frequency synthesis then you're wasting a clock buffer.

  FPGA, SystemVerilog, Designs

• Clock deskew is also known as phase alignment.

  FPGA, SystemVerilog, Designs

• only required if you need clock deskewing, that is a known, fixed phase relationship between the MMCM input clock and the MMCM output clock

  FPGA, SystemVerilog, Designs

• BUFG isn't needed if the source clock pin is connected directly to the MMCM and nothing else, but it is needed if there is other logic connected directly to the source clock pin.

  fpga - Using MMCM/PLL source clock pin elsewhere in design breaks timing - Electrical Engineering Stack Exchange

• 1. the problematic constraints in the .xdc generated by the clock wizard were commented out automatically, and 2. an additional BUFG was placed after the IBUF following the clock port, which wasn't present with the single ended option

  fpga - Using MMCM/PLL source clock pin elsewhere in design breaks timing - Electrical Engineering Stack Exchange

• create_clock – period 10ns –name sys_clk –waveform {0 5} [get_ports sys_clk]

  Adam Taylor’s MicroZed Chronicles, Part 70: Constraints—Introduction to timing and defining a clock

• those that enter through an I/O pin

  Adam Taylor’s MicroZed Chronicles, Part 70: Constraints—Introduction to timing and defining a clock

• Negative slack means metastability is an issue because of a timing violation.

  Adam Taylor’s MicroZed Chronicles, Part 70: Constraints—Introduction to timing and defining a clock

• parsed header is not output as a stream, but as a PMT dictionary

  Packet Header Parser - GNU Radio