zeroasiccorp/logikbench: Digital logic benchmark suite ·
github.com · 6,113 words · saved by 1 readers
Digital logic benchmark suite
Why LogikBench LogikBench is a large hybrid benchmark suite of human authored and AI generated Verilog RTL circuits. Use cases includes objective evaluation of EDA algorithms/tools, PDKs, architectures, model/LLMs, compute infrastructure, (and more...). "Sunlight is said to be the best of disinfectants." --Supreme Court Justice Louis Brandeis Challenge LogikBench Solution "No Spec CPU for RTL" 250 robust Verilog RTL benchmark circuits (>1M LOC) Circuit diversity Broad mix of circuit types, sizes, and source origins Size diversity Per-circuit parameterization across multiple scales Trust Docume
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