Writing Slow Code (On Purpose) | Axel Feldmann
Every few years, my research group holds a “slow code challenge.” The objective is to write the code with the lowest achieved instructions per cycle (IPC) when run on a pre-selected x86 server. This seems absurd! And fundamentally, it is. However, there is some method to this madness. CPU designers work hard to achieve the highest possible IPC… even for very inefficient code. It is (intentionally) not easy to write very high IPC code. Therefore, the slow code challenge is a tricky exercise that forces you to think about how CPUs work and how to exploit their sharp edges. The rules of our challenge are somewhat vague (it’s more about presenting solutions that are within the “spirit of the challenge”), but I’ll try to formalize them. Valid entries should be: In this post, I will discuss a couple different approaches to this challenge. Additional note: all performance results come from an AMD EPYC 7763 64-Core Processor (Zen3). This is a reasonable question! The key distinction here is be