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RL isn’t the silver bullet for AI-powered chip design

zach.be · 1,028 words · saved by 2 readers

My most popular post of all time was about why Y Combinator is wrong about LLMs for chip design. Put simply, I don’t think LLMs are able to generate high-performance or high-efficiency chip designs, because the process of designing high-performance chips is incredibly unforgiving. The entire “vibe coding” trend is about generating a large quantity of mediocre code, while the challenge of chip design is writing a relatively small amount of extremely high-quality, extremely performance-sensitive code in a specialized language called Verilog. And so far, I’ve been proven right. By and large, LLMs kinda suck at writing Verilog. Never fear, though! Reinforcement learning (aka RL) will come to the rescue, right? RL has proven invaluable when it comes to making normally error-prone AI agents solve unforgiving tasks, from playing board games to constructing complex mathematical proofs. Why can’t we leverage RL systems to train AI models to write the sort of high-quality, performance-sensitive

RL isn’t the silver bullet for AI-powered chip design But new EDA tools could change that… zach Sep 25, 2025 20 8 Share My most popular post of all time was about why Y Combinator is wrong about LLMs for chip design . Put simply, I don’t think LLMs are able to generate high-performance or high-efficiency chip designs, because the process of designing high-performance chips is incredibly unforgiving. The entire “vibe coding” trend is about generating a large quantity of mediocre code, while the challenge of chip design is writing a relatively small amount of extremely high-quality, extremely pe

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