UVM Tutorial for Candy Lovers – 1. Overview – ClueLogic

Accellera’s recently released UVM may change the future of verification, as verification methodology seems to be consolidated in this UVM. This post will provide a simple tutorial on this new verification methodology. Rather than focusing on AXI, OCP, or other system buses in existence, this tutorial will be based on the hypothetical example of a jelly-bean generator. The test bench will generate many jelly-bean flavors in a constrained random manner and the system will evaluate palatable flavors. This does not require the knowledge of any system bus. The verification components used in the process will be described below. The left figure shows the relationship of the verification components. The jelly_bean_taster is the design-under-test (DUT) module. The jelly_bean_sequencer will create jelly-bean recipes and send them to the jelly_bean_driver. From the information provided in the recipe, the driver creates jelly beans. The driver passes the jelly beans through the jelly-bean interfa

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• Simon Guo